Figure 117. General Port Pin Schematic Diagram(1)
PUExn
PUD
Q
D
DDxn
Q CLR
WDx
RDx
RESET
OCxn
Q
D
Pxn
PORTxn
ODxn
Q CLR
WPx
RRx
IDxn
RESET
SLEEP
SYNCHRONIZER
RPx
D
Q
D
L
Q
PINxn
Q
Q
CLK I/O
PUD:
PULLUP DISABLE
WDx:
RDx:
WPx:
RRx:
RPx:
WRITE DDRx
PUExn:
OCxn:
ODxn:
IDxn:
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
SLEEP:
CLK I/O
:
Note:
1. See Boundary-scan descriptin for details.
Boundary-scan and the Two-
wire Interface
The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the
scan-chain; Two-wire Interface Enable – TWIEN. As shown in Figure 118, the TWIEN
signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital
port pins. A general scan cell as shown in Figure 122 is attached to the TWIEN signal.
Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordi-
nary scan support for digital port pins suffice for connectivity tests. The only reason
for having TWIEN in the scan path, is to be able to disconnect the slew-rate control
buffer when doing boundary-scan.
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will
lead to drive contention.
230
ATmega32(L)
2503J–AVR–10/06
ATMEL [ ATMEL ]
