ATmega640/1280/1281/2560/2561
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
Pin Change Mask Register 2 –
PCMSK2
Bit
7
PCINT23
R/W
0
6
PCINT22
R/W
0
5
PCINT21
R/W
0
4
PCINT20
R/W
0
3
PCINT19
R/W
0
2
PCINT18
R/W
0
1
PCINT17
R/W
0
0
PCINT16
R/W
0
PCMSK2
Read/Write
Initial Value
• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16
Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corre-
sponding I/O pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change
interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
Pin Change Mask Register 1 –
PCMSK1
Bit
7
PCINT15
R/W
0
6
PCINT14
R/W
0
5
PCINT13
R/W
0
4
PCINT12
R/W
0
3
PCINT11
R/W
0
2
PCINT10
R/W
0
1
PCINT9
R/W
0
0
PCINT8
R/W
0
PCMSK1
Read/Write
Initial Value
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the correspond-
ing I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt
is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt
on the corresponding I/O pin is disabled.
Pin Change Mask Register 0 –
PCMSK0
Bit
7
6
5
4
3
2
1
0
PCINT7
R/W
0
PCINT6
R/W
0
PCINT5
R/W
0
PCINT4
R/W
0
PCINT3
R/W
0
PCINT2
R/W
0
PCINT1
R/W
0
PCINT0
R/W
0
PCMSK0
Read/Write
Initial Value
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the correspond-
ing I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
79
2549A–AVR–03/05
ATMEL [ ATMEL ]
