ATmega640/1280/1281/2560/2561
External Interrupts
The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23..0 pins
are configured as outputs. This feature provides a way of generating a software
interrupt.
The Pin change interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin
change interrupt PCI1 if any enabled PCINT15:8 toggles and Pin change interrupts
PCI0 will trigger if any enabled PCINT7..0 pin toggles. PCMSK2, PCMSK1 and
PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin
change interrupts on PCINT23 ..0 are detected asynchronously. This implies that these
interrupts can be used for waking the part also from sleep modes other than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the External Interrupt Control Registers –
EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is con-
figured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an
I/O clock, described in “Clock Systems and their Distribution” on page 39. Low level
interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies
that these interrupts can be used for waking the part also from sleep modes other than
Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 39.
Pin Change Interrupt
Timing
An example of timing of a pin change interrupt is shown in Figure 32.
Figure 32.
pin_lat
pcint_in_(0)
PCINT(0)
clk
0
x
D
Q
pcint_syn
pcint_setflag
PCIF
pin_sync
PCINT(0) in PCMSK(x)
LE
clk
clk
PCINT(n)
pin_lat
pin_sync
pcint_in_(n)
pcint_syn
pcint_setflag
PCIF
75
2549A–AVR–03/05
ATMEL [ ATMEL ]
