ATmega640/1280/1281/2560/2561
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices,
these bits must be written to zero when TCCRnC is written.
Timer/Counter1 – TCNT1H
and TCNT1L
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1[7:0]
TCNT1H
TCNT1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
Timer/Counter3 – TCNT3H
and TCNT3L
Bit
7
6
5
4
3
2
1
0
TCNT3[15:8]
TCNT3[7:0]
TCNT3H
TCNT3L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
Timer/Counter4 – TCNT4H
and TCNT4L
Bit
7
6
5
4
3
2
1
0
TCNT4[15:8]
TCNT4[7:0]
TCNT4H
TCNT4L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
Timer/Counter5 – TCNT5H
and TCNT5L
Bit
7
6
5
4
3
2
1
0
TCNT5[15:8]
TCNT5[7:0]
TCNT5H
TCNT5L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give
direct access, both for read and for write operations, to the Timer/Counter unit 16-bit
counter. To ensure that both the high and low bytes are read and written simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit tempo-
rary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 137.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing
a compare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following
timer clock for all compare units.
163
2549A–AVR–03/05
ATMEL [ ATMEL ]
