ATmega8U2/16U2/32U2
Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
7.4.1
General Purpose I/O Registers
The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global vari-
ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.5
Register Description
7.5.1
EEARH and EEARL – The EEPROM Address Register
Bit
15
14
13
12
11
10
9
8
0x22 (0x42)
0x21 (0x41)
–
–
–
–
EEAR11
EEAR10
EEAR9
EEAR8
EEARH
EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
7
R
6
R
5
R
4
R
3
R/W
R/W
X
2
R/W
R/W
X
1
R/W
R/W
X
0
R/W
R/W
X
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
X
X
X
X
X
X
X
X
• Bits 15:12 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 11:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
7.5.2
EEDR – The EEPROM Data Register
Bit
0x20 (0x40)
7
6
5
4
3
2
1
0
MSB
LSB
R/W
0
EEDR
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
20
7799D–AVR–11/10
ATMEL [ ATMEL ]
