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ATMEGA16U2-MUR 参数 Datasheet PDF下载

ATMEGA16U2-MUR图片预览
型号: ATMEGA16U2-MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8/16 / 32K Butes [8-bit Microcontroller with 8/16/32K Butes of ISP Flash]
分类和应用: 微控制器异步传输模式PCATM
文件页数/大小: 310 页 / 4432 K
品牌: ATMEL [ ATMEL ]
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ATmega8U2/16U2/32U2  
7.5.3  
EECR – The EEPROM Control Register  
Bit  
7
6
5
EEPM1  
R/W  
X
4
EEPM0  
R/W  
X
3
EERIE  
R/W  
0
2
EEMPE  
R/W  
0
1
EEPE  
R/W  
X
0
EERE  
R/W  
0
0x1F (0x3F)  
Read/Write  
Initial Value  
EECR  
R
0
R
0
• Bits 7:6 – Res: Reserved Bits  
These bits are reserved bits and will always read as zero.  
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits  
The EEPROM Programming mode bit setting defines which programming action that will be trig-  
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old  
value and program the new value) or to split the Erase and Write operations in two different  
operations. The Programming times for the different modes are shown in Table 7-1. While EEPE  
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00  
unless the EEPROM is busy programming.  
Table 7-1.  
EEPROM Mode Bits  
Programming  
EEPM1  
EEPM0  
Time  
3.4 ms  
1.8 ms  
1.8 ms  
Operation  
0
0
1
1
0
1
0
1
Erase and Write in one operation (Atomic Operation)  
Erase Only  
Write Only  
Reserved for future use  
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable  
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing  
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-  
rupt when EEPE is cleared.  
• Bit 2 – EEMPE: EEPROM Master Programming Enable  
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.  
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the  
selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been  
written to one by software, hardware clears the bit to zero after four clock cycles. See the  
description of the EEPE bit for an EEPROM write procedure.  
• Bit 1 – EEPE: EEPROM Programming Enable  
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address  
and data are correctly set up, the EEPE bit must be written to one to write the value into the  
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-  
wise no EEPROM write takes place. The following procedure should be followed when writing  
the EEPROM (the order of steps 3 and 4 is not essential):  
21  
7799D–AVR–11/10  
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