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ATMEGA16U2-MUR 参数 Datasheet PDF下载

ATMEGA16U2-MUR图片预览
型号: ATMEGA16U2-MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器具有ISP功能的Flash 8/16 / 32K Butes [8-bit Microcontroller with 8/16/32K Butes of ISP Flash]
分类和应用: 微控制器异步传输模式PCATM
文件页数/大小: 310 页 / 4432 K
品牌: ATMEL [ ATMEL ]
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ATmega8U2/16U2/32U2  
7. AVR Memories  
This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR archi-  
tecture has two main memory spaces, the Data Memory and the Program Memory space. In  
addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three  
memory spaces are linear and regular.  
7.1  
In-System Reprogrammable Flash Program Memory  
The ATmega8U2/16U2/32U2 contains 8K/16K/32K bytes On-chip In-System Reprogrammable  
Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash  
is organized as 4K x 16, 8K x 16. For software security, the Flash Program memory space is  
divided into two sections, Boot Program section and Application Program section.  
The Flash memory has an endurance of at least 100,000 write/erase cycles. The  
ATmega8U2/16U2/32U2 Program Counter (PC) is 16 bits wide, thus addressing the  
8K/16K/32K program memory locations. The operation of Boot Program section and associated  
Boot Lock bits for software protection are described in detail in “Memory Programming” on page  
246. “Memory Programming” on page 246 contains a detailed description on Flash data serial  
downloading using the SPI pins or the debugWIRE interface.  
Constant tables can be allocated within the entire program memory address space (see the LPM  
– Load Program Memory instruction description and ELPM - Extended Load Program Memory  
instruction description).  
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-  
ing” on page 12.  
16  
7799D–AVR–11/10  
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