ATmega8U2/16U2/32U2
6.6.1
SPH and SPL – Stack Pointer High and Low Register
Bit
15
14
13
12
11
10
9
8
0x3E (0x5E)
0x3D (0x5D)
SP15
SP7
7
SP14
SP6
6
SP13
SP5
5
SP12
SP4
4
SP11
SP3
3
SP10
SP2
2
SP9
SP1
1
SP8
SP0
0
SPH
SPL
Read/Write
Initial Value
R/W
R/W
0
R/W
R/W
0
R/W
R/W
1
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
1
1
1
1
1
1
1
1
6.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
12
7799D–AVR–11/10
ATMEL [ ATMEL ]
