ATmega169P
15.4 Register Description
15.4.1
GTCCR – General Timer/Counter Control Register
Bit
7
6
–
5
–
4
–
3
–
2
–
1
PSR2
R/W
0
0
PSR10
R/W
0
0x23 (0x43)
Read/Write
Initial Value
TSM
R/W
0
GTCCR
R
0
R
0
R
0
R
0
R
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,
and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
137
8018A–AVR–03/06
ATMEL [ ATMEL ]
