Table 20-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Table 20-7. Compare Output Mode, Phase Correct PWM Mode(1)
COM2B1
COM2B0
Description
Normal port operation, OC2B disconnected.
Reserved
0
0
0
1
Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.
1
1
0
1
Set OC2B on Compare Match when up-counting. Clear OC2B on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 180 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 20-8. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 177).
Table 20-8. Waveform Generation Mode Bit Description
Timer/Counter
Mode of
Operation
Update of
OCRx at
TOV Flag
Mode
WGM2
WGM1
WGM0
TOP
Set on(1)(2)
0
0
0
0
Normal
0xFF
Immediate
TOP
MAX
PWM, Phase
1
0
0
1
0xFF
BOTTOM
Correct
2
3
4
0
0
1
1
1
0
0
1
0
CTC
OCRA
0xFF
–
Immediate
BOTTOM
–
MAX
MAX
–
Fast PWM
Reserved
PWM, Phase
5
1
0
1
OCRA
TOP
BOTTOM
Correct
6
7
1
1
1
1
0
1
Reserved
–
–
–
Fast PWM
OCRA
BOTTOM
TOP
Notes: 1. MAX= 0xFF
2. BOTTOM= 0x00
190
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
