Figure 17-12. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clk
I/O
clk
(clkT/n8)
I/O
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn(FPWM)
and ICFn(if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
17.11 Register Description
17.11.1 TCCR1A – Timer/Counter 1 Control Register A
Bit
7
COM1A1
R/W
6
COM1A0
R/W
5
COM1B1
R/W
4
COM1B0
R/W
3
COM1C1
R/W
2
COM1C0
R/W
1
WGM11
R/W
0
0
WGM10
R/W
0
TCCR1A
TCCR3A
TCCR4A
(0x80)
Read/Write
Initial Value
0
0
0
0
0
0
17.11.2 TCCR3A – Timer/Counter 3 Control Register A
Bit
7
COM3A1
R/W
6
COM3A0
R/W
5
COM3B1
R/W
4
COM3B0
R/W
3
COM3C1
R/W
2
COM3C0
R/W
1
WGM31
R/W
0
0
WGM30
R/W
0
(0x90)
Read/Write
Initial Value
0
0
0
0
0
0
17.11.3 TCCR4A – Timer/Counter 4 Control Register A
Bit
7
COM4A1
R/W
6
COM4A0
R/W
5
COM4B1
R/W
4
COM4B0
R/W
3
COM4C1
R/W
2
COM4C0
R/W
1
WGM41
R/W
0
0
WGM40
R/W
0
(0xA0)
Read/Write
Initial Value
0
0
0
0
0
0
17.11.4 TCCR5A – Timer/Counter 5 Control Register A
Bit
7
6
5
4
3
2
1
0
158
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
