AT90PWM2/3/2B/3B
16.5.3
Fifty Percent Waveform Configuration
When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the
PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRn-
SBH/L and OCRnRBH/L registers in OCRnSAH/L and OCRnRAH/L registers. So it is not
necessary to program OCRnSAH/L and OCRnRAH/L registers.
16.6 Update of Values
To avoid unasynchronous and incoherent values in a cycle, if an update of one of several values
is necessary, all values are updated at the same time at the end of the cycle by the PSC. The
new set of values is calculated by sofware and the update is initiated by software.
Figure 16-11. Update at the end of complete PSC cycle.
Regulation Loop
Calculation
Writting in
PSC Registers
Request for
an Update
Software
PSC
Cycle
Cycle
With Set i
Cycle
With Set i
Cycle
With Set i
With Set i
Cycle
With Set j
End of Cycle
The software can stop the cycle before the end to update the values and restart a new PSC
cycle.
16.6.1
Value Update Synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to
LOCK and AUTOLOCK configuration bits, the new whole set of values can be taken into
account after the end of the PSC cycle.
When AUTOLOCK configuration is selected, the update of the PSC internal registers will be
done at the end of the PSC cycle if the Output Compare Register RB has been the last written.
The AUTOLOCK configuration bit is taken into account at the end of the first PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers
will be done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK and AUTOLOCK are PSOCn,
POM2, OCRnSAH/L, OCRnRAH/L, OCRnSBH/L and OCRnRBH/L.
See these register’s description starting on page 162.
When set, AUTOLOCK configuration bit prevails over LOCK configuration bit.
See “PSC 0 Configuration Register – PCNF0” on page 163.
16.7 Enhanced Resolution
Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve
the normal resolution is based on Flank Width Modulation (also called Fractional Divider).
Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the
139
4317J–AVR–08/10
ATMEL [ ATMEL ]
