AT77C105A [Preliminary]
VDD_IO = 2.3V to 3.6V
Table 10. Digital Inputs
Logic Compatibility
CMOS
Name
Parameter
Conditions
Test Level
Min
Typ
Max
Unit
Low level input current without pull-
up device(1)
IIL
VI = 0V
I
1
µA
High level input current without
pull-down device(1)
IIH
VI = VDD_IO
I
IV
I
1
1
µA
µA
V
Tri-state output leakage without
pull-up/down device(1)
IIOZ
VIL
VI = 0V or VDD_IO
0.5
VDD_IO
Low level input voltage(1)
High level input voltage(1)
Schmitt trigger hysteresis(1)
(1)
0.6
VDD_IO
VIH
I
V
(1)
0.06
VDD_IO
0.09
VDD_IO
VHYST
IV
V
Table 11. Digital Outputs
Logic Compatibility
CMOS
Min
Name
Parameter
Conditions
Test Level
Typ
Max
Unit
I
OL = 4 mA
0.10
VDD_IO
VOL
Low level output voltage
VDD _IO = 2.3V to
3.6V
I
V
(1)
I
OH = -4 mA
VOH
High level output voltage
VDD_IO = 2.3V to
3.6V
I
0.90 VDD
V
Input/Output Voltage Level Compatibility
The I/O voltage level compatibility is set by the power voltage driven on the VDD_IO
pad. For 1.8V level compatibility, connect VDD_IO to a 1.8V power supply.
7
5419A–BIOM–01/05
ATMEL [ ATMEL ]
