CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continu-
ous read operation without the need of additional address sequences. To perform a
continuous read, an opcode of 68H or E8H must be clocked into the device followed by 24
address bits and 32 don’t care bits. The first six bits of the 24-bit address sequence are
reserved for upward and downward compatibility to larger and smaller density devices (see
Notes under “Command Sequence for Read/Write Operations” diagram). The next nine
address bits (PA8-PA0) specify which page of the main memory array to read, and the last
nine bits (BA8-BA0) of the 24-bit address sequence specify the starting byte address within
the page. The 32 don’t care bits that follow the 24 address bits are needed to initialize the read
operation. Following the 32 don’t care bits, additional clock pulses on the SCK pin will result in
serial data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t care
bits, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one
page to the beginning of the next page). When the last bit in the main memory array has been
read, the device will continue reading back at the beginning of the first page of memory. As
with crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR
specification. The Continuous Array Read bypasses both data buffers and leaves the contents
of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from
any one of the 512 pages in the main memory, bypassing the data buffer and leaving the con-
tents of the buffer unchanged. To start a page read, the 8-bit opcode, 52H or D2H, must be
clocked into the device followed by 24 address bits and 32 don’t care bits. In the
AT45DB011B, the first six address bits are reserved for larger density devices (see Notes on
page 15), the next nine address bits (PA8-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’t care
bits which follow the 24 address bits are sent to initialize the read operation. Following the 32
don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial
output) pin. The CS pin must remain low during the loading of the opcode, the address bits,
and the reading of data. When the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the beginning of the same page. A low-
to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from the data buffer using an opcode of 54H or D4H. To
perform a buffer read, the eight bits of the opcode must be followed by 15 don’t care bits, nine
address bits, and eight don’t care bits. Since the buffer size is 264 bytes, nine address bits
(BFA8- BFA0) are required to specify the first byte of data to be read from the buffer. The CS
pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and
the reading of data. When the end of the buffer is reached, the device will continue reading
back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the
read operation and tri-state the SO pin.
4
AT45DB011B
1984H–DFLSH–10/04
ATMEL [ ATMEL ]
