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90USB1287-16AU 参数 Datasheet PDF下载

90USB1287-16AU图片预览
型号: 90USB1287-16AU
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机具有ISP功能的Flash和USB控制器64 / 128K字节 [Microcontroller with 64/128K Bytes of ISP Flash and USB Controller]
分类和应用: 微控制器
文件页数/大小: 434 页 / 3172 K
品牌: ATMEL [ ATMEL ]
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AT90USB64/128  
The TWINT Flag is set in the following situations:  
• After the TWI has transmitted a START/REPEATED START condition.  
• After the TWI has transmitted SLA+R/W.  
• After the TWI has transmitted an address byte.  
• After the TWI has lost arbitration.  
• After the TWI has been addressed by own slave address or general call.  
• After the TWI has received a data byte.  
• After a STOP or REPEATED START has been received while still addressed as a Slave.  
• When a bus error has occurred due to an illegal START or STOP condition.  
20.6 TWI Register Description  
20.6.1  
TWI Bit Rate Register – TWBR  
Bit  
7
6
TWBR6  
R/W  
0
5
TWBR5  
R/W  
0
4
TWBR4  
R/W  
0
3
TWBR3  
R/W  
0
2
TWBR2  
R/W  
0
1
TWBR1  
R/W  
0
0
TWBR0  
R/W  
0
TWBR7  
R/W  
0
TWBR  
Read/Write  
Initial Value  
• Bits 7..0 – TWI Bit Rate Register  
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency  
divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator  
Unit” on page 223 for calculating bit rates.  
20.6.2  
TWI Control Register – TWCR  
Bit  
7
6
TWEA  
R/W  
0
5
TWSTA  
R/W  
0
4
TWSTO  
R/W  
0
3
2
TWEN  
R/W  
0
1
0
TWIE  
R/W  
0
TWINT  
R/W  
0
TWWC  
TWCR  
Read/Write  
Initial Value  
R
0
R
0
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a  
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,  
to generate a stop condition, and to control halting of the bus while the data to be written to the  
bus are written to the TWDR. It also indicates a write collision if data is attempted written to  
TWDR while the register is inaccessible.  
• Bit 7 – TWINT: TWI Interrupt Flag  
This bit is set by hardware when the TWI has finished its current job and expects application  
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the  
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT  
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-  
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag  
starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-  
tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this  
flag.  
• Bit 6 – TWEA: TWI Enable Acknowledge Bit  
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to  
one, the ACK pulse is generated on the TWI bus if the following conditions are met:  
225  
7593A–AVR–02/06  
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