bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 20-8. Arbitration Between Two Masters
START
Master A Loses
Arbitration, SDAA SDA
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
20.5 Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 20-9. All registers
drawn in a thick line are accessible through the AVR data bus.
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ATMEL [ ATMEL ]
