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90USB1287-16AU 参数 Datasheet PDF下载

90USB1287-16AU图片预览
型号: 90USB1287-16AU
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机具有ISP功能的Flash和USB控制器64 / 128K字节 [Microcontroller with 64/128K Bytes of ISP Flash and USB Controller]
分类和应用: 微控制器
文件页数/大小: 434 页 / 3172 K
品牌: ATMEL [ ATMEL ]
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The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an  
associated address comparator that looks for the slave address (or general call address if  
enabled) in the received serial address. If a match is found, an interrupt request is generated.  
• Bits 7..1 – TWA: TWI (Slave) Address Register  
These seven bits constitute the slave address of the TWI unit.  
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit  
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.  
20.6.6  
TWI (Slave) Address Mask Register – TWAMR  
Bit  
7
6
5
4
TWAM[6:0]  
R/W  
3
2
1
0
TWAMR  
Read/Write  
Initial Value  
R/W  
R/W  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R
0
0
0
0
• Bits 7..1 – TWAM: TWI Address Mask  
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can  
mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask  
bit is set to one then the address match logic ignores the compare between the incoming  
address bit and the corresponding bit in TWAR. Figure 20-10 shows the address match logic in  
detail.  
Figure 20-10. TWI Address Match Logic, Block Diagram  
TWAR0  
Address  
Match  
Address  
Bit 0  
TWAMR0  
Address Bit Comparator 0  
Address Bit Comparator 6..1  
• Bit 0 – Res: Reserved Bit  
This bit is reserved and will always read as zero.  
20.7 Using the TWI  
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like  
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,  
the application software is free to carry on other operations during a TWI byte transfer. Note that  
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in  
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-  
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in  
order to detect actions on the TWI bus.  
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application  
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current  
228  
AT90USB64/128  
7593A–AVR–02/06  
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