欢迎访问ic37.com |
会员登录 免费注册
发布采购

90USB1287-16AU 参数 Datasheet PDF下载

90USB1287-16AU图片预览
型号: 90USB1287-16AU
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机具有ISP功能的Flash和USB控制器64 / 128K字节 [Microcontroller with 64/128K Bytes of ISP Flash and USB Controller]
分类和应用: 微控制器
文件页数/大小: 434 页 / 3172 K
品牌: ATMEL [ ATMEL ]
 浏览型号90USB1287-16AU的Datasheet PDF文件第222页浏览型号90USB1287-16AU的Datasheet PDF文件第223页浏览型号90USB1287-16AU的Datasheet PDF文件第224页浏览型号90USB1287-16AU的Datasheet PDF文件第225页浏览型号90USB1287-16AU的Datasheet PDF文件第227页浏览型号90USB1287-16AU的Datasheet PDF文件第228页浏览型号90USB1287-16AU的Datasheet PDF文件第229页浏览型号90USB1287-16AU的Datasheet PDF文件第230页  
1. The device’s own slave address has been received.  
2. A general call has been received, while the TWGCE bit in the TWAR is set.  
3. A data byte has been received in Master Receiver or Slave Receiver mode.  
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial  
Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one  
again.  
• Bit 5 – TWSTA: TWI START Condition Bit  
The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire  
Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition  
on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is  
detected, and then generates a new START condition to claim the bus Master status. TWSTA  
must be cleared by software when the START condition has been transmitted.  
• Bit 4 – TWSTO: TWI STOP Condition Bit  
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire  
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-  
matically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.  
This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed  
Slave mode and releases the SCL and SDA lines to a high impedance state.  
• Bit 3 – TWWC: TWI Write Collision Flag  
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is  
low. This flag is cleared by writing the TWDR Register when TWINT is high.  
• Bit 2 – TWEN: TWI Enable Bit  
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to  
one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the  
slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI  
transmissions are terminated, regardless of any ongoing operation.  
• Bit 1 – Res: Reserved Bit  
This bit is a reserved bit and will always read as zero.  
• Bit 0 – TWIE: TWI Interrupt Enable  
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-  
vated for as long as the TWINT Flag is high.  
20.6.3  
TWI Status Register – TWSR  
Bit  
7
6
TWS6  
R
5
TWS5  
R
4
TWS4  
R
3
TWS3  
R
2
1
TWPS1  
R/W  
0
0
TWPS0  
R/W  
0
TWS7  
TWSR  
Read/Write  
Initial Value  
R
1
R
0
1
1
1
1
• Bits 7..3 – TWS: TWI Status  
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status  
codes are described later in this section. Note that the value read from TWSR contains both the  
5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-  
226  
AT90USB64/128  
7593A–AVR–02/06  
 复制成功!