Figure 44. IEN1 Register
IEN1 (S:E8h)
Interrupt Enable Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
-
EADC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
-
-
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ADC Interrupt Enable bit
1
0
EADC
-
Clear to disable the ADC interrupt.
Set to enable the ADC interrupt.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = xxxx x000b
bit addressable
92
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
