Table 63. ADCLK Register
ADCLK (S:F2h)
ADC Clock Prescaler
7
-
6
-
5
-
4
3
2
1
0
PRS 4
PRS 3
PRS 2
PRS 1
PRS 0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4-0
-
The value read from these bits are indeterminate. Do not set these bits.
Clock Prescaler
Fadc = Fcpuclock/(4*PRS)) in X1 mode
PRS4:0
Fadc=Fcpuclock/(2*PRS) in X2 mode
Reset Value = XXX0 0000b
Table 64. ADDH Register
ADDH (S:F5h Read Only)
ADC Data High Byte Register
7
6
5
4
3
2
1
0
ADAT 9
ADAT 8
ADAT 7
ADAT 6
ADAT 5
ADAT 4
ADAT 3
ADAT 2
Bit
Bit
Number
Mnemonic Description
ADC result
ADAT9:2
7 - 0
bits 9-2
Reset Value = 00h
Table 65. ADDL Register
ADDL (S:F4h Read Only)
ADC Data Low Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
ADAT 1
ADAT 0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1-0
-
The value read from these bits are indeterminate. Do not set these bits.
ADC result
bits 1-0
ADAT1:0
Reset Value = 00h
88
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
