AT89C5115
Registers
Figure 43. IEN0 Register
IEN0 (S:A8h)
Interrupt Enable Register
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic Description
Enable All Interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
7
EA
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its interrupt enable bit.
PCA Interrupt Enable
6
5
4
3
2
1
0
EC
ET2
ES
Clear to disable the PCA interrupt.
Set to enable the PCA interrupt.
Timer 2 Overflow Interrupt Enable bit
Clear to disable Timer 2 overflow interrupt.
Set to enable Timer 2 overflow interrupt.
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 Overflow Interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
ET1
EX1
ET0
EX0
External Interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 Overflow Interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External Interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
bit addressable
91
4128F–8051–05/06
ATMEL [ ATMEL ]
