Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register. This register also contains a global disable bit
which must be cleared to disable all the interrupts at the same time.
Each interrupt source can also be individually programmed to one of four priority levels
by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the
bit values and priority levels associated with each combination.
Table 66. Priority Level bit Values
IPH.x
IPL.x
Interrupt Level Priority
0
0
1
1
0
1
0
1
0 (Lowest)
1
2
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt but not by another
low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of the higher priority level is serviced. If interrupt requests of the same priority
level are received simultaneously, an internal polling sequence determines which
request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, See Table 67.
Table 67. Interrupt Priority Within Level
Interrupt Name
External interrupt (INT0)
Timer0 (TF0)
Interrupt Address Vector
Priority Number
0003h
000Bh
0013h
001Bh
0033h
0023h
002Bh
0043h
1
2
3
4
5
6
7
9
External interrupt (INT1)
Timer 1 (TF1)
PCA (CF or CCFn)
UART (RI or TI)
Timer 2 (TF2)
ADC (ADCI)
90
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
