Table 71. IPH1 Register
IPH1 (S:F7h)
Interrupt high priority Register 1
7
-
6
-
5
-
4
-
3
-
2
1
0
-
POVRH
PADCH
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
-
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer Overrun Interrupt Priority Level Most Significant bit
POVRH POVRLPriority level
0
0
1
1
0
1
0
1
Lowest
2
POVRH
Highest
ADC Interrupt Priority Level Most Significant bit
PADCH PADCLPriority level
0
0
1
1
0
1
0
1
Lowest
1
0
PADCH
Highest
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = XXXX X000b
96
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
