Table 69. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
7
-
6
-
5
-
4
-
3
-
2
1
0
-
POVRL
PADCL
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Timer Overrun Interrupt Priority Level Less Significant bit
Refer to PI2CH for priority level.
POVRL
PADCL
-
ADC Interrupt Priority Level Less Significant bit
Refer to PSPIH for priority level.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = XXXX X000b
bit addressable
94
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
