AT89C5115
Registers
Table 61. ADCF Register
ADCF (S:F6h)
ADC Configuration
7
6
5
4
3
2
1
0
CH 7
CH 6
CH 5
CH 4
CH 3
CH 2
CH 1
CH 0
Bit
Bit
Number
Mnemonic Description
Channel Configuration
7 - 0
CH 0:7
Set to use P1.x as ADC input.
Clear to use P1.x as standart I/O port.
Reset Value = 0000 0000b
Table 62. ADCON Register
ADCON (S:F3h)
ADC Control Register
7
-
6
5
4
3
2
1
0
PSIDLE
ADEN
ADEOC
ADSST
SCH2
SCH1
SCH0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from these bits are indeterminate. Do not set these bits.
Pseudo Idle Mode (Best Precision)
PSIDLE Set to put in idle mode during conversion
Clear to convert without idle mode.
Enable/Standby Mode
5
4
ADEN
Set to enable ADC
Clear for Standby mode.
End Of Conversion
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
ADEOC
Must be cleared by software.
Start and Status
3
ADSST
SCH2:0
Set to start an A/D conversion.
Cleared by hardware after completion of the conversion
Selection of Channel to Convert
See Table 60
2-0
Reset Value = X000 0000b
87
4128F–8051–05/06
ATMEL [ ATMEL ]
