AT89C5115
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Table 60. Selected Analog input
SCH2
SCH1
SCH0
Selected Analog Input
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range (See section
“AC-DC”).
Clock Selection
The ADC clock is the same as CPU.
The maximum clock frequency is defined in the DC parmeter for A/D converter. A pres-
caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.
if PRS = 0 then FADC = Fperiph / 64
if PRS > 0 then FADC = Fperiph / 2 x PRS
Figure 40. A/D Converter Clock
ADC Clock
CPU
CLOCK
Prescaler ADCLK
÷ 2
A/D
Converter
CPU Core Clock Symbol
ADC Standby Mode
IT ADC management
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN
in ADCON register. In this mode the power dissipation is reduced.
An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit
EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.
85
4128F–8051–05/06
ATMEL [ ATMEL ]
