Registers
Table 43. T2CON Register
T2CON (S:C8h)
Timer 2 Control Register
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic Description
Timer 2 Overflow Flag
TF2 is not set if RCLK=1 or TCLK = 1.
Must be cleared by software.
Set by hardware on Timer 2 overflow.
7
6
TF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
EXF2
Must be cleared by software.
Receive Clock bit
5
4
RCLK
TCLK
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
3
EXEN2
Timer 2 Run Control bit
Clear to turn off Timer 2.
Set to turn on Timer 2.
2
1
TR2
Timer/Counter 2 Select bit
Clear for timer operation (input from internal clock system: fOSC).
Set for counter operation (input from T2 input pin).
C/T2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
Timer 2 overflow.
Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
0
CP/RL2#
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
bit addressable
64
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
