Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the
WDT duration.
Table 49. Machine Cycle Count
S2
0
S1
0
S0
0
Machine Cycle Count
214 - 1
0
0
1
215 - 1
0
1
0
216 - 1
0
1
1
217 - 1
1
0
0
218 - 1
1
0
1
219 - 1
1
1
0
220 - 1
1
1
1
221 - 1
To compute WD Timeout, the following formula is applied:
2 ∧
2
14
6 × 2
(2 × 2
)
Note:
Svalue represents the decimal value of (S2 S1 S0)
Find Hereafter computed Timeout values for fOSCXTAL = 12 MHz in X1 mode
Table 50. Timeout Computation
S2
0
S1
0
S0
0
fOSC=12 MHz
16.38 ms
32.77 ms
65.54 ms
131.07 ms
262.14 ms
524.29 ms
1.05 s
fOSC=16MHz
12.28 ms
24.57 ms
49.14 ms
98.28 ms
196.56 ms
393.12 ms
786.24 ms
1.57 s
fOSC=20 MHz
9.82 ms
0
0
1
19.66 ms
39.32 ms
78.64 ms
157.28 ms
314.56 ms
629.12 ms
1.25 s
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
2.10 s
68
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
