AT89C5115
Watchdog Timer
T89C5115 contains a powerful programmable hardware Watchdog Timer (WDT) that
automatically resets the chip if it software fails to reset the WDT before the selected time
interval has elapsed. It permits large Timeout ranging from 16ms to 2s @fOSC = 12 MHz
in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis-
ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST
register with no instruction between the two writes. When the Watchdog Timer is
enabled, it will increment every machine cycle while the oscillator is running and there is
no way to disable the WDT except through reset (either hardware reset or WDT over-
flow reset). When WDT overflows, it will generate an output RESET pulse at the RST
pin. The RESET pulse duration is 96xTOSC, where TOSC=1/fOSC. To make the best use of
the WDT, it should be serviced in those sections of code that will periodically be exe-
cuted within the time required to prevent a WDT reset
Note:
When the watchdog is enable it is impossible to change its period.
Figure 31. Watchdog Timer
Decoder
RESET
WR
Control
WDTRST
Enable
14-bit Counter
7-bit Counter
Outputs
Fwd Clock
WDTPRG
RESET
67
4128F–8051–05/06
ATMEL [ ATMEL ]
