Table 38. TMOD Register
TMOD (S:89h)
Timer/Counter Mode Control Register
7
6
5
4
3
2
1
0
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Bit
Bit
Number
Mnemonic Description
Timer 1 Gating Control bit
Clear to enable Timer 1 whenever TR1 bit is set.
7
GATE1
Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
Timer 1 Counter/Timer Select bit
6
5
C/T1#
M11
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
Timer 1 Mode Select bits
M11 M01 Operating mode
0
0
0
1
Mode 0: 8-bit Timer/Counter (TH1) with 5bit prescaler (TL1).
Mode 1: 16-bit Timer/Counter.
4
M01
1
1
1
0
Mode 3: Timer 1 halted. Retains count.
Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1)
Timer 0 Gating Control bit
3
2
1
GATE0
C/T0#
M10
Clear to enable Timer 0 whenever TR0 bit is set.
Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.
Timer 0 Counter/Timer Select bit
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 0 Mode Select bit
M10 M00 Operating mode
0
0
1
0
1
0
Mode 0: 8-bit Timer/Counter (TH0) with 5bit prescaler (TL0).
Mode 1: 16-bit Timer/Counter.
Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2)
M00
0
1
1
Mode 3: TL0 is an 8-bit Timer/Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
Reset Value = 0000 0000b
Notes: 1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.
Table 39. TH0 Register
TH0 (S:8Ch)
Timer 0 High Byte Register
7
6
5
4
3
2
1
0
Bit
Bit
Number
Mnemonic Description
7:0
High Byte of Timer 0
Reset Value = 0000 0000b
60
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
