AT89C5132
Figure 16-12. Command Line Controller Block Diagram
Data Converter
// -> Serial
CRC7
Generator
TX Pointer
5-byte FIFO
MMCMD
Write
CTPTR
MMCON0.4
TX COMMAND Line
Finished State Machine
MMINT.5
EOCI
CFLCK
MMSTA.0
CMDEN
MMCON1.0
MCMD
Command Transmitter
MMSTA.2
MMSTA.1
CRC7S RESPFS
Data Converter
Serial -> //
CRC7 and Format
Checker
RX Pointer
17-byte FIFO
MMCMD
Read
CRPTR
MMCON0.5
RX COMMAND Line
Finished State Machine
MMINT.6
EORI
RESPEN RFMT CRCDIS
MMCON1.1 MMCON0.1 MMCON0.0
Command Receiver
16.5.1
Command Transmitter
To send a command to the card, the user must load the command index (1 byte) and argument
(4 Bytes) in the command transmit FIFO using the MMCMD register. Before starting transmis-
sion by setting and clearing the CMDEN bit in MMCON1 register, the user must first configure:
•
•
•
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
RFMT bit in MMCON0 register to indicate the response size expected.
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the response will
be computed or not. In order to avoid CRC error, CRCDIS may be set for responses that do
not include CRC7.
Figure 16-13 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicating that
write to the FIFO is locked. This mechanism is implemented to avoid command over-run.
The end of the command transmission is signalled by the EOCI flag in MMINT register becoming
set. This flag may generate an MMC interrupt request as detailed in Section "Interrupt", page 96.
The end of the command transmission also resets the CFLCK flag.
The user may abort command loading by setting and clearing the CTPTR bit in MMCON0 regis-
ter which resets the write pointer to the transmit FIFO.
89
4173E–USB–09/07
ATMEL [ ATMEL ]
