AT89C5132
Table 21. Status for Master Receiver Mode
Application Software Response
To SSCON
SSSTO SSI
Status
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
A START condition has
08h
Write SLA+R
X
0
0
X
SLA+R will be transmitted.
SLA+R will be transmitted.
SLA+W will be transmitted.
been transmitted
Write SLA+R
Write SLA+W
X
X
0
0
0
0
X
X
A repeated START
condition has been
transmitted
10h
Logic will switch to master transmitter mode.
TWI bus will be released and not addressed slave
mode will be entered.
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
0
1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
Arbitration lost in
SLA+R or NOT ACK
bit
38h
40h
A START condition will be transmitted when the bus
becomes free.
Data Byte will be received and NOT ACK will be
returned.
SLA+R has been
transmitted; ACK has
been received
Data Byte will be received and ACK will be returned.
Repeated START will be transmitted.
No SSDAT action
No SSDAT action
1
0
0
1
0
0
X
X
SLA+R has been
transmitted; NOT ACK
has been received
STOP condition will be transmitted and SSSTO flag
will be reset.
48h
50h
58h
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
No SSDAT action
Read data Byte
Read data Byte
1
0
0
1
0
0
0
0
0
X
0
1
Data Byte will be received and NOT ACK will be
returned.
Data Byte has been
received; ACK has
been returned
Data Byte will be received and ACK will be returned.
Repeated START will be transmitted.
Read data Byte
Read data Byte
1
0
0
1
0
0
X
X
Data Byte has been
received; NOT ACK
has been returned
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Read data Byte
1
1
0
X
141
4173E–USB–09/07
ATMEL [ ATMEL ]
