AT89C5132
Figure 20-4. Format and States in the Master Receiver Mode
MR
Successful reception
from a slave transmitter
S
SLA
R
A
Data
A
Data
A
P
08h
40h
50h
58h
Next transfer started with
a repeated start condition
S
SLA
R
10h
W
Not acknowledge received
after the slave address
A
P
MT
48h
Arbitration lost in slave
address or data Byte
Other master
continues
Other master
continues
A or A
A
38h
A
38h
Arbitration lost and
addressed as slave
Other master
continues
To corresponding
states in slave mode
68h 78h B0h
Any number of data Bytes and their associated
acknowledge bits
From master to slave
From slave to master
Data
nnh
A
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
137
4173E–USB–09/07
ATMEL [ ATMEL ]
