Figure 6-4. PLL Block Diagram and Symbol
PFILT
CHP
PLLCON.1
PLLEN
N divider
OSC
Up
Vref
N6:0
PLL
Clock
CLOCK
PFLD
VCO
Down
PLOCK
PLLCON.0
R divider
R9:0
PLL
CLOCK
OSCclk × (R + 1)
PLLclk = ----------------------------------------------
N + 1
PLL Clock Symbol
Figure 6-5. PLL Filter Connection
PFILT
R
C2
C1
VSS
VSS
6.3.2
PLL Programming
The PLL is programmed using the flow shown in Figure 6-6. As soon as clock generation is
enabled, the user must wait until the lock indicator is set to ensure the clock output is stable. The
PLL clock frequency will depend on the audio interface clock frequencies.
Figure 6-6. PLL Programming Flow
PLL
Programming
Configure Dividers
N6:0 = xxxxxxb
R9:0 = xxxxxxxxxxb
Enable PLL
PLLRES = 0
PLLEN = 1
PLL Locked?
PLOCK = 1?
6.4
Registers
Table 1. CKCON Register
14
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
