AT89C5132
CKCON (S:8Fh) – Clock Control Register
7
6
5
-
4
3
-
2
1
0
TWIX2
WDX2
SIX2
T1X2
T0X2
X2
Bit
Bit Number Mnemonic Description
Two-Wire Clock Control Bit
7
TWIX2
Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent).
Clear to select the peripheral clock as TWI clock input (X2 dependent).
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
6
5
4
3
2
WDX2
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2 independent).
Clear to select the peripheral clock as UART clock input (X2 dependent)..
SIX2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by two as Timer 1 clock input (X2 independent).
Clear to select the peripheral clock as Timer 1 clock input (X2 dependent).
T1X2
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by two as timer 0 clock input (X2 independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
1
0
T0X2
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER = FOSC
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
/2).
Reset Value = 0000 000Xb
Table 2. PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
7
-
6
5
4
3
2
1
0
N6
N5
N4
N3
N2
N1
N0
Bit
Bit Number Mnemonic Description
Reserved
The value read from this bit is always 0. Do not set this bit.
7
-
PLL N Divider
6-0
N6:0
7-bit N divider.
Reset Value = 0000 0000b
15
4173E–USB–09/07
ATMEL [ ATMEL ]
