Table 3. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
7
6
5
-
4
-
3
2
-
1
0
R1
R0
PLLRES
PLLEN
PLOCK
Bit
Bit Number Mnemonic Description
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
7 - 6
5 - 4
R1:0
-
Reserved
The values read from these Bits are always 0. Do not set these Bits.
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
3
2
1
PLLRES
-
Reserved
The values read from this bit is always 0. Do not set this bit.
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
PLLEN
PLL Lock Indicator
0
PLOCK
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Reset Value = 0000 1000b
Table 4. PLLRDIV Register
PLLRDIV (S:EFh) – PLL R Divider Register
7
6
5
4
3
2
1
0
R9
R8
R7
R6
R5
R4
R3
R2
Bit
Bit Number Mnemonic Description
PLL Most Significant Bits R Divider
7 - 0
R9:2
8 MSB of the 10-bit R divider.
Reset Value = 0000 0000b
16
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
