Bit
Bit
Number
Mnemonic Description
Running Flag
0
NFRUN
Set by hardware to signal that it is currently running.
Cleared by hardware to signal it is not running.
Reset Value = 0000 0000b
Table 213. NFECC Register
NFECC (1.A4h) – Nand Flash Controller ECC 1 and ECC 2 Register
7
6
5
4
3
2
1
0
NFED7
NFED6
NFED5
NFED4
NFED3
NFED2
NFED1
NFED0
Bit
Bit
Number
Mnemonic Description
Nand Flash ECC 6-byte Data FIFO
Read Mode
7-0
NFED7:0
Sequential reading returns 2 ECC values of 3 bytes.
Write Mode
Writing any data resets the ECC engine and the FIFO manager.
Reset Value = 0000 0000b
Table 214. NFINT Register
NFINT (1.A5h) – Nand Flash Controller Interrupt Register
7
6
5
4
3
2
1
0
-
-
-
SMCTI
ILGLI
ECCRDYI
ECCERRI
STOPI
Bit
Bit
Number
Mnemonic Description
Reserved
7-5
4
-
The value read from these bits is always 0. Do not set these bits.
SmartMedia Card Transition Interrupt Flag
SMCTI
ILGLI
Set by hardware every time SMCD bit in NFSTA is toggling.
Shall be cleared by software.
ILLEGAL operation Interrupt Flag
3
2
1
0
Set by hardware when an illegal operation is performed.
Shall be cleared by software.
ECC Ready Interrupt Flag
Set by hardware when the ECCs (6 bytes) are ready for operation.
This bit is set/clear even if the spare zone is automatically managed (ECCEN).
Shall be cleared by software.
ECCRDYI
ECCERRI
STOPI
ECC Error Interrupt Flag
Set by hardware when a bad ECC is seen.
Shall be cleared by software.
Stop Interrupt Flag
Set by hardware when a running (NFRUN= 1) to not running (NFRUN= 0)
transition is met (end of page, end of data transfer, …)
Shall be cleared by software.
Reset Value = 0000 0000b
188
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
