AT85C51SND3Bx
Table 210. NFDAT Register
NFDAT (1.A2h) – Nand-Flash Controller Data Access Register
7
6
5
4
3
2
1
0
DATD7
DATD6
DATD5
DATD4
DATD3
DATD2
DATD1
DATD0
Bit
Bit
Number
Mnemonic Description
Data Byte
7-0
DATD7:0
Writing data sends a data to the currently selected NF.
Reading data gets the data returned by the last read cycle.
Reset Value = 0000 0000b
Table 211. NFDATF Register
NFDATF (1.A3h) – Nand-Flash Controller Data Access and Fetch Next Data Register
7
6
5
4
3
2
1
0
DATFD7
DATFD6
DATFD5
DATFD4
DATFD3
DATFD2
DATFD1
DATFD0
Bit
Bit
Number
Mnemonic Description
Data Byte
Writing data sends a data to the currently selected NF.
Reading data gets the data returned by the last read cycle and relaunch a read
cycle on the currently selected NF.
7-0
DATFD7:0
Reset Value = 0000 0000b
Table 212. NFSTA Register
NFSTA (1.98h) – Nand Flash Controller Status Register
7
6
5
4
3
2
1
0
SMCD
SMLCK
-
NFEOP
NECC2
NECC1
NECC0
NFRUN
Bit
Bit
Number
Mnemonic Description
SmartMediaCard Detection Flag
7
SMCD
Set by hardware when the SMINS input is High.
Cleared by hardware when the SMINS input is Low.
SmartMedia Card Lock Flag
6
5
SMLCK
-
Set by hardware when the SMC is write-protected.
Cleared by hardware when the SMC is not write-protected.
Reserved
The value read from this bit is always 0. Do not set this bit.
End Of Page Flag
4
NFEOP
NECC2:0
Set by hardware when the controller stops at the end of the page.
clear by hardware if the controller did not reach the end of the page.
Number of ECC Bits
3-1
Set/clear by hardware. See Section “ECC Error Management” for more details.
187
7632A–MP3–03/06