AT85C51SND3Bx
The control logic of the UVCC pad outputs 2 signals:
•
The “session_valid” signal is active high when the voltage on the UVCC pin is higher
or equal to 1.4V.
•
The “Va_Vbus_valid” signal is active high when the voltage on the UVCC pin is
higher or equal to 4.4V.
In the Host mode, the VBUS flag follows the next hysteresis rule:
•
•
VBUS is set when the voltage on the UVCC pin is higher or equal to 4.4 V.
VBUS is cleared when the voltage on the UVCC pin is lower than 1.4 V.
In the Peripheral mode, the VBUS flag follows the next rule:
•
•
VBUS is set when the voltage on the UVCC pin is higher or equal to 1.4 V.
VBUS is cleared when the voltage on the UVCC pin is lower than 1.4 V.
The VBUSTI interrupt is triggered at each transition of the VBUS flag.
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7632A–MP3–03/06
ATMEL [ ATMEL ]
