Table 105. UDPADDH Register
UDPADDH (1.E4h) – USB Dual Port Ram Direct Access High Register
7
6
5
4
3
2
1
0
DPACC
-
-
-
-
DPADD10:8
Bit
Bit
Number
Mnemonic Description
DPRAM Direct Access Bit
Set this bit to directly read the content the Dual-Port RAM (DPR) data through
the UEDATX or UPDATX registers. See Section “Memory Access Capability” for
more details.
7
DPACC
Clear this bit for normal operation and access the DPR through the endpoint
FIFO.
Reserved
6-3
2-0
-
The value read from these bits is always 0. Do not set these bits.
DPRAM Address High Bit
DPADD10:8
DPADD10:8 is the most significant part of DPADD. The least significant part is
provided by the UDPADDL register.
Reset Value = 0000 0000b
Table 106. UDPADDL Register
UDPADDL (1.E5h) – USB Dual Port Ram Direct Access High Register
7
6
5
4
3
2
1
0
DPADD7:0
Bit
Bit
Number
Mnemonic Description
DPRAM Address Low Bit
7-0
DPADD7:0
DAPDD7:0 is the least significant part of DPADD. The most significant part is
provided by the UDPADDH register.
Reset Value = 0000 0000b
Table 107. OTGCON Register
OTGCON (1.E6h) – USB OTG Control Register
7
6
5
4
3
2
1
0
0
-
HNPREQ
SRPREQ
SRPSEL
VBUSHWC VBUSREQ VBUSRQC
Bit
Bit
Number
Mnemonic Description
OTGCON pagination
7
6
0
-
This bit must be cleared to access the OTGCON register.
Reserved
The value read from these bits is always 0. Do not set these bits.
96
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
