AT85C51SND3Bx
Speed Control
Device Mode
When the USB interface is configured in device mode, the speed selection (Full Speed
or High Speed) is performed automatically by the USB controller during the USB Reset.
A the end of the USB reset, the USB controller automatically enables or disables high-
speed terminations and pull-up.
Note:
It is possible to force the speed of the protocol, through the SPDCONF1:0 bits. For nor-
mal operations, SPDCONF1:0 must be cleared.
For all other operations (e.g. running in Full-Speed only), SPDCONF1:0 shall be written
before enabling the controller (USBE set), in order to avoid any side effects. The follow-
ing table summarizes all the possible configurations:
Table 100. Speed configuration
Mode
Peripheral
Host
SPDCONF1:0 Description
Normal Mode (default)
00
01
10
Use High-Speed pad in Full-Speed or High-Speed.
Full-Speed only mode (Full-Speed pad)
Shall be done before setting USBE.
High-Speed only mode (High-Speed pad)
Shall be used in debug mode.
11
Full-Speed only mode (High-Speed pad)
Use Full-Speed pad
XX
Clearing USBE resets SPDCONF1:0.
Host Mode
When the USB interface is configured in host mode, internal pull down resistors are acti-
vated on both DMF and DPF lines.
Memory Access
Capability
The CPU has the capability to directly access to the USB internal memory (DPRAM).
The memory access mode is performed using UDPADDH and UDPADDL registers.
To enter in this mode:
•
•
USBE bit must be cleared.
DPACC bit and the base address DPADD10:0 must be set.
The DPACC bit and DPADD10:0 field can be used by the firmware even if the USBE bit
is cleared.
Then, a read or a write in UEDATX (device mode) or in UPDATX (host mode) is per-
formed according to DPADD10:0 and the base address DPADD10:0 field is
automatically increased. The endpoint FIFO pointers and the value of the UxNUM regis-
ters are discarded in this mode.
The aim of this functionality is to use the DPRAM as extra-memory.
89
7632A–MP3–03/06
ATMEL [ ATMEL ]
