When using this mode, there is no influence over the USB controller.
Unused
[DPADDH – DPADDL]
Endpoint 1 to N
Endpoint 0
USB DPRAM
Memory Management
The controller only supports the following memory allocation management:
The reservation of a Pipe or an Endpoint can only be made in the growing order
(Pipe/Endpoint 0 to the last Pipe/Endpoint). The firmware shall thus configure them in
the same order.
The reservation of a Pipe or an Endpoint “ki” is done when its ALLOC bit is set. Then,
the hardware allocates the memory and insert it between the Pipe/Endpoints “ki-1” and
“ki+1”. The “ki+1” Pipe/Endpoint memory “slides” up and its data is lost. Note that the “ki+2
and upper Pipe/Endpoint memory does not slide.
”
Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear neither its
ALLOC bit, nor its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the
firmware should clear ALLOC. Then, the “ki+1” Pipe/Endpoint memory automatically
“slides” down. Note that the “ki+2” and upper Pipe/Endpoint memory does not slide.
The following figure illustrates the allocation and reorganization of the USB memory in a
typical example:
Figure 54. Allocation and reorganization USB memory flow
Free memory
5
Free memory
Free memory
5
Free memory
5
4
5
4
Conflict
4
3
Lost memory
4
EPEN=0
(ALLOC=1)
3 (bigger size)
2
2
2
2
1
0
1
0
1
0
1
0
EPEN=1
ALLOC=1
Pipe/Endpoints
activation
Pipe/Endpoint
Disable
Free its memory
(ALLOC=0)
Pipe/Endpoint
Activatation
90
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
