AT85C51SND3Bx
Bit
Bit
Number
Mnemonic Description
HNP Request Bit
Set to initiate the HNP when the controller is in the Device mode (B).
Set to accept the HNP when the controller is in the Host mode (A).
Cleared by hardware after the HNP completion.
5
HNPREQ
SRP Request Bit
4
3
2
SRPREQ
SRPSEL
Set to initiate the SRP when the controller is in Device mode.
Cleared by hardware when the controller is initiating a SRP.
SRP Selection Bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
VBus Hardware Control Bit
VBUSHWC
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
VBUS Request Bit
Set to assert the UVCON pin in order to enable the VBUS power supply
generation. This bit shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
1
0
VBUSREQ
VBUSRQC
VBUS Request Clear Bit
Set to deassert the UVCON pin in order to enable the VBUS power supply
generation. This bit shall be used when the controller is in the Host mode.
Cleared by hardware immediately after the set.
Reset Value = 0000 0000b
Table 108. OTGTCON Register
OTGTCON (1.E6h) – USB OTG Timer Control Register
7
6
5
4
3
2
1
0
1
PAGE1:0
-
-
VALUE2:0
Bit
Bit
Number
Mnemonic Description
OTGTCON Pagination
7
1
This bit must be set to access the OTGTCON register.
Timer Page Access Bit
6-5
4-3
2-0
PAGE1:0
-
Set/clear to access a special timer register.
See Section “OTG Timers Customizing” for more details.
Reserved
The value read from these bits is always 0. Do not set these bits.
Value Bit
VALUE2:0
Set to initialize the new value of the timer.
See Section “OTG Timers Customizing” for more details.
Reset Value = 0000 0000b
97
7632A–MP3–03/06
ATMEL [ ATMEL ]
