banks, clearing the FIFOCON bit will switch to the next bank. The RXOUTI and FIFO-
CON bits are then updated by hardware in accordance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware
can read data from the bank, and cleared by hardware when the bank is empty.
Example with 1 OUT data bank
DATA
OUT
NAK
DATA
(to bank 0)
ACK
HW
OUT
ACK
HW
(to bank 0)
RXOUTI
SW
SW
read data from CPU
BANK 0
FIFOCON
SW
read data from CPU
BANK 0
Example with 2 OUT data banks
DATA
OUT
DATA
(to bank 1)
ACK
HW
OUT
ACK
(to bank 0)
HW
RXOUTI
SW
SW
read data from CPU
BANK 0
SW
FIFOCON
read data from CPU
BANK 1
“Autoswitch” Mode
In this mode, the clear of the FIFOCON bit is performed automatically by hardware each
time the Endpoint bank is empty. The firmware has to check if the next bank is empty or
not before reading the next data. On RXOUTI interrupt, the firmware reads a complete
bank. A new interrupt will be generated each time the current bank contains data to
read.
The acknowledge of the RXOUTI interrupt is always performed by software.
Detailed Description
standard Mode Without
AUTOSW
In this mode (AUTOSW cleared), the data are read by the CPU, following the next flow:
•
When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if
enabled (RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or
FIFOCON, depending on the software architecture,
•
•
The CPU acknowledges the interrupt by clearing RXOUTI,
The CPU can read the number of byte (N) in the current bank (N=BYCT),
108
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
