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85C51SND3B1 参数 Datasheet PDF下载

85C51SND3B1图片预览
型号: 85C51SND3B1
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片数字音频解码器 - 编码器与USB 2.0接口 [Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface]
分类和应用: 解码器编码器
文件页数/大小: 263 页 / 3620 K
品牌: ATMEL [ ATMEL ]
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the host sends a SETUP command (SET_ADDRESS(addr)),  
the firmware records that address in UADD, but keep ADDEN cleared,  
the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet),  
then, the firmware can enable the USB device address by setting ADDEN. The only  
accepted address by the controller is the one stored in UADD.  
ADDEN and UADD shall not be written at the same time.  
UADD contains the default address 00h after a power-up or USB reset.  
ADDEN is cleared by hardware:  
after a power-up reset,  
when an USB reset is received,  
or when the macro is disabled (USBE cleared)  
When this bit is cleared, the default device address 00h is used.  
Suspend, Wake-Up and  
Resume  
After a period of 3 ms during which the USB line was inactive, the controller switches to  
the full-speed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firm-  
ware may then set the FRZCLK bit.  
The CPU can also, depending on software architecture, enter in the idle mode to lower  
again the power consumption.  
There are two ways to recover from the “Suspend” mode:  
First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle  
mode.  
Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE  
set). Then, as soon as an non-idle signal is seen by the controller, the WAKEUPI  
interrupt is triggered. The firmware shall then clear the FRZCLK bit to restart the  
transfer.  
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the  
WAKEUPI interrupt is triggered as soon as there are non-idle patterns on the data lines.  
Thus, the WAKEUPI interrupt can occurs even if the controller is not in the “suspend”  
mode.  
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is  
cleared by hardware.  
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is  
cleared by hardware.  
Detach  
The reset value of the DETACH bit is 1.  
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit.  
If the USB device controller is in full-speed mode, setting DETACH will disconnect  
the pull-up on the D+ or D- pad (depending on full or low speed mode selected).  
Then, clearing DETACH will connect the pull-up on the D+ or D- pad.  
104  
AT85C51SND3Bx  
7632A–MP3–03/06  
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