AT85C51SND3Bx
Control Read
The next figure shows a control read transaction. The USB controller has to manage the
simultaneous write requests from the CPU and the USB host:
SETUP
SETUP
HW
DATA
STATUS
USB line
IN
IN
OUT
NAK
OUT
SW
RXSTPI
RXOUTI
TXINI
HW
SW
SW
HW
SW
Wr Enable
HOST
Wr Enable
CPU
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data written by the CPU are erased,
and clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
Once the OUT status stage has been received, the USB controller waits for a SETUP
request. The SETUP request have priority over any other request and has to be
ACK’ed. This means that any other flag should be cleared and the fifo reset when a
SETUP is received.
WARNING: the byte counter is reset when the OUT Zero Length Packet is received.
The firmware has to take care of this.
OUT Endpoint
Management
OUT packets are sent by the host. All the data can be read by the CPU, which acknowl-
edges or not the bank when it is empty.
Overview
The Endpoint must be configured first.
“Manual” Mode
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This trig-
gers an interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB
interrupt by clearing the RXOUTI bit. The Firmware read the data and clear the FIFO-
CON bit in order to free the current bank. If the OUT Endpoint is composed of multiple
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7632A–MP3–03/06
ATMEL [ ATMEL ]
