AT85C51SND3Bx
•
•
The CPU can read the data from the current bank (“N” read of UEDATX),
The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
–
–
after “N” read of UEDATX,
as soon as RWAL is cleared by hardware.
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current
one is being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may
be already ready and RXOUTI is set immediately.
Standard Mode with AUTOSW
In this mode (AUTOSW set), the flow operation is the same as Section “standard Mode
Without AUTOSW”, page 108, with the exception that the CPU does not have to free the
bank (FIFOCON cleared): this will automatically be done when the CPU read the last
byte of the bank.
•
•
•
EPINTx (RXOUTE set, RXOUTI set) or polling on RXOUTI=1 or FIFOCON=1,
The CPU acknowledges the interrupt by clearing RXOUTI,
The CPU read the number of byte (N) in the current bank (N=BYCT) (or already
knows the number “N” of bytes at each packet),
•
The CPU can read the data from the current bank (“N” read of UEDATX, or can read
while RWAL is set).
A clear of FIFOCON does not have any effects in this mode.
Using the DFC with AUTOSW
In this mode (AUTOSW set, DFC programmed), the data are handled by the DFC with-
out any intervention from the CPU. The flow is:
•
•
programming of the DFC,
poll End Of Transfer from the DFC.
The bank switching is automatically done: when a bank is emptied, it is freed and the
switch occurs. If the End Of Transfer occurs while the bank is not emptied, the CPU has
the responsibility to free it.
The CPU shall not use UEDATX or the byte counter BYCT in this mode. A clear of
FIFOCON does not have any effects in this mode.
If a ZLP is received, it will be filtered by the USB device controller, and the flag ZLP-
SEEN is set.
Using the DFC without
AUTOSW
In this mode (AUTOSW cleared, DFC programmed), the data are handled by the DFC
but the CPU have to acknowledge each bank read.
•
•
•
•
•
programming of the DFC,
EPINTx (RXOUTE set, RXOUTI set) or polling on RXOUTI=1 or FIFOCON=1,
The CPU acknowledges the interrupt by clearing RXOUTI,
poll the wait of the transfer: (while RWAL is set: wait),
Clear FIFOCON which frees the bank and switch to the next one.
IN Endpoint Management IN packets are sent by the USB device controller, upon an IN request from the host. All
the data can be written by the CPU, which acknowledge or not the bank when it is full.
Overview
The Endpoint must be configured first.
“Manual” Mode
The TXINI bit is set by hardware when the current bank becomes free. This triggers an
interrupt if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU
109
7632A–MP3–03/06
ATMEL [ ATMEL ]
