writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the
data. If the IN Endpoint is composed of multiple banks, this also switches to the next
data bank. The TXINI and FIFOCON bits are automatically updated by hardware
regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware
can write data to the bank, and cleared by hardware when the bank is full.
Example with 1 IN data bank
NAK
DATA
(bank 0)
IN
ACK
HW
IN
TXINI
SW
SW
write data from CPU
BANK 0
FIFOCON
SW
SW
write data from CPU
BANK 0
Example with 2 IN data banks
DATA
(bank 0)
DATA
(bank 1)
IN
ACK
HW
IN
ACK
TXINI
SW
SW
SW
write data from CPU
BANK0
write data from CPU
BANK 0
write data from CPU
BANK 1
FIFOCON
SW
SW
“Autoswitch” Mode
In this mode, the clear of the FIFOCON bit is performed automatically by hardware each
time the Endpoint bank is full. The firmware has to check if the next bank is empty or not
before writing the next data. On TXINI interrupt, the firmware fills a complete bank. A
new interrupt will be generated each time the current bank becomes free.
Detailed Description
Standard Mode without
AUTOSW
In this mode (AUTOSW cleared), the data are written by the CPU, following the next
flow:
•
When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled
(TXINE set) and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending
the software architecture choice,
•
•
The CPU acknowledges the interrupt by clearing TXINI,
The CPU can write the data into the current bank (write in UEDATX),
110
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
