AT8xC51SND2C
Register
Table 101. AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
-
4
3
2
1
0
SDA
SCL
AUDCDOUT AUDCDIN AUDCCLK AUDCCS
KIN0
Bit
Bit
Number
Mnemonic
Description
TWI Serial Data
7
6
SDA
SDA is the bidirectional Two Wire data line.
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
SCL
-
5
4
3
2
Not used.
AUDCDOUT Audio Dac SPI Data Output.
AUDCDIN Audio Dac SPI Data Input
AUDCCLK Audio Dac SPI clock
Audio Dac Chip select
1
0
AUDCCS
KIN0
Set to deselect DAC
Clear to select DAC
Keyboard Input Interrupt.
Reset Value = 1111 1111b
91
4341D–MP3–04/05
ATMEL [ ATMEL ]
