AT8xC51SND2C
Signal
Description
LMSMIN1
Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to
disable
LMSMIN2
RMSMIN1
RMSMIN2
Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to
disable
Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to
disable
Note:
Refer to DAC_MC register Table 110. for signal description
Master Clock and Sampling
Frequency Selection
The following table describes the different modes available for master clock and sam-
pling frequency selection by setting OVRSEL bit in DAC_CSFC register (refer to Table
111.).
Table 97. Master Clock selection
OVRSEL
Master Clock
256 x FS
0
1
384 x FS
The selection of input sample size is done using the NBITS 1:0 in DAC_MISC register
(refer to Table 112.) according to Table 98.
Table 98. Input Sample Size Selection
NBITS 1:0
Format
16 bits
18 bits
20 bits
00
01
10
The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer
to Table 112.) according to Table 99.
Table 99. Format Selection
DINTSEL 1:0
Format
00
01
1x
I2S Justified
MSB Justified
LSB Justified
De-emphasis and dither
enable
The circuit features a de-emphasis filter for the playback channel. To enable the de-
emphasis filtering, DEEMPEN must be set to high.
Likewise, the dither option (added in the playback channel) is enabled by setting the
DITHEN signal to High.
89
4341D–MP3–04/05
ATMEL [ ATMEL ]
